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February 8, 2019  Organization    Organization  February 8, 2019 
February 8, 2019  Introduction, Models of computation  [Par09]  Introduction  February 8, 2019 
February 15, 2019  Architecture synthesis and scheduling  [Ger99]  Architectural Synthesis  February 13, 2012 
February 15, 2019  Overlapped scheduling  [Ger98]  
February 22, 2019 
No lecture, holiday week  
March 1 & 8, 2019  Algorithm transformations  [Par95]  Transformations Addendum  February 19, 2012 
March 8, 2019  Fixedpoint design  [Bou08]  FixedPoint Design  March 9, 2019 
March 15, 2019  The Arx RTL Language and Toolset 
[Hof07] 
Arx 
March 9, 2018 
March 22, 2019  The CORDIC Algorithm  [And98] and [Loe00]  CORDIC  March 16, 2018 
March 22, 2019  Polyphase implementation of multirate filters  [Lan02] and [Vai90]  Polyphase implementation  March 16, 2018 
March 29, 2019 
Multiplierless filter design  [Hew00], [Vor07], [Aks14] and [Kot03]  Multiplierless Filter Design  March 20, 2017 
March 29, 2019  Modern DSP Architectures 
[Anj11] 
DSP Architectures  March 20, 2017 
April 5, 2019  Code generation  Sections III and IV of [Bha00]  Code Generation  April 5, 2019 
April 5, 2019  Case study: simultaneous design of processor and compiler  [Goo05]     
April 5, 2019  FFT basics + FFT Hardware Structures  Sections 9.2+9.3 of [Chi12], [He98]  FFT basics and FFT hardware  April 6, 2018 
  Software synthesis  Sections I and II of [Bha00] No lecure and not part of the examination for academic year 20182019 
Software Synthesis  April 6, 2016 
Caption of Figure 6: last subscript of y should be n1 instead of n.
Right column of Page 856: Read Figure 9(b) where 9(a) is mentioned and vice versa.
Contents of Figure 17: In order to be consistent with next figures, rewrite "x = a  b" and "y = a  b + c * d".
Those interested in a detailed analysis of the probability density function of the truncation error after multiplication can consult the followin noncompulsory paper:
Ahmadi, A. and M. Zwolinski, FixedPoint Multiplication: A Probabilistic BitPattern View, Microelectronics Reliability, Vol. 51(4), pp 790796, (April 2011). Online copy (only in UT domain).
You can skip Seciton 11.3 (2D FIR filters).
Page 203, halfway bottom paragraph: twice add a minus sign to 2's exponent (so 2**n should become 2**n).
Page 204, Equation 11.10: the "close" parenthesis with exponent 2 should move to the end of the equation.
You can skip Section 6.5.3 on the efficient computation of the iterationperiod bound.
You can skip Section 12.4.3 on forcedirected scheduling.
Optional text!
Correction for Equation 6: there should not be a factor 2 in front of h_LP(m).
You can skip Sections 6 (folding) and 8 (relaxed lookahead).
Comments on Figure 6. The issue is that unfolding can improve the processor utilization. The explanation in the paper is not correct.
The schedule shown in Figure 6(b) is rate optimal i.e. it repeats at the iterationperiod bound (T0min) value of 3. In this period, the total of the computations to be performed is 9 (4 operations of 2 and 1 of 1) time units. The lower bound on the number of processors is 3 (=9/3). However, this bound cannot be met. The reason is that the schedule needs to repeat every 3 time units. This means that a separate processor is necessary for each of the operations A to D that take two time units (a processor that would execute two of them would require an iteration period of 4). One has an average processor utilization of 75% (9/12).
Figure 6(c) shows a schedule of the graph after 2unfolding. The unfolded graph contains 2 iterations of the original graph. This schedule is also rate optimal which means that the 2 iterations are executed in 6 time units. The optimal number of processor in this situation would be again 3 (=18/6). There now exists a schedule that reaches 100% processor utilization (the available 6 time units per processor can now be filled optimally with operations of 2 time units).
In Figure 6(b), the operations A0, B0, C0, D0 and E0 belong to one iteration. The schedule has an iteration period of 3 (A1 starts 3 time units after A0, etc.) a latency of 7 (output on E0) and a span of 8 (end of D0).
In Figure 6(c), the operations A0/A1, B0/B1, C0/C1, D0/D1 and E0/E1 belong to one iteration. The schedule has an iteration period of 6 (A2 starts 6 time units after A0, etc.) and a latency and span of 12 (output on E1).
Comments on Figure 9(a). According to me, two inequalities are incorrect: r(A2)  r(M1) <= 2 and r(M4)  r(A3) <= 1.
Optional text.
Only study Section 1 (until page 6); the rest is optional.
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