The goals of this project are to explore the design space for a small algorithm to be implemented on silicon. Currently, the design space exploration amounts to optimize the design and observe the relation between area and time. In the future, power will be added as a third parameter to be optimized.

The description below refers to various file names. These files are not available on-line. Once you have logged in, execute the command get-sec to get them or copy them from the directory /home/practice/vlsisd/exercise/modules/sec.

The Filter

VHDL Files

• The file second-ent.vhd contains the entity for the design. The file second-parallel-arch.vhd describes a 1-to-1 mapping of the DFG to hardware. The entire filter except for the multipliers is described in a behavioral way.
• The file mymult.vhd contains a behavioral descriptions of a multiplier. One of the objectives of this project is to replace this multiplier by a structural description of your own.
• The file tb-second.vhd (needs to be compiled for VHDL 93) contains the entities for the testbench:
• The entity testvec_second, the test-vector generator, provides the clock and reset signals, as well as the inputs for the filter. The input signal xn is read from a file called second.in. The version of the file that you receive, is a input file for the calculation of an impulse response, i.e. a maximally positive value as a first sample followed by zeroes. The output yn is stored in a file second.out. A reference output second.ref contains the expected output when calculating the impulse response. You can verify the correctness of your implementation by comparing second.out with second.ref (use e.g. the Unix diff command to compare files). The entity has been prepared for to deal with wide range of different implementations. You can adapt it to your implementation by providing the correct values for its generic parameters for iteration period, latency and clock period.
• The entity tb_second instantiates the design and the test-vector generator and interconnects them. One needs to define suitable configurations for this top-level entity in order to simulate different versions of the design. This configuration can set the generics of testvec_second.

Synthesis

Exercise SEC-1: Synthesis, Pre-Syntheis and Post-Synthesis Simulation

• Perform a pre-synthesis simulation of the filter and verify that the file second.out contains the correct data. Make use of the configuration as given in the file config-second-pre.vhd. Note: It may be that Modelsim only writes the contents of second.out on disk after terminating the current simulation.
• Synthesize the provided description that is the 1-to-1 implementation of the DFG, for a few different clock periods using the script generate-design. Record the (time, area) pairs as a reference for comparison with other design variant that you will make. It also makes sense to record which part of the area is used by multipliers, adders and other hardware.
• Perform a post-synthesis simulation of the filter. Use the configuration as given in config_second_post40.vhd as a template.

Exercise SEC-2: Design-Space Exloration

Here are some suggestions and points to take into account:

• Replace the behavioral description of the multiplier by a structural one. This is optional if you are working alone, but compulsory for teams consisting of at least two students. Remember that the multiplier operands are signed.
• What improvements can be achieved by retiming and pipelining?
• The largest subblock in the design is the multiplier and reducing the number of multipliers is likely to save area. Make a design containing 1, 2 or 3 multipliers that uses multiple clock cycles per sample (how many?). Such a design will normally require more registers and multiplexers than the fully parallel design. Try to quantify this overhead by studying the log files.
• Of course, the correctness of each design alternative has to be verified by both a pre-synthesis and a post-synthesis simulation.
• Make an area-versus-time plot of all design alternatives. Do you see a hyperbolic relation (one often claims that the area-time product for VLSI designs is constant)? Identify the Pareto-optimal solutions.

Deliverables