VLSI System Design (121146)

Instructors

• Sabih Gerez: Lectures and examination.

Organization

• This course will not be taught for the time being as its contents are under discussion. Motivated students can follow this course on the basis of an individual program. In such a case, you should contact me first and make an agreement on how to proceed.
• Starting from the academic year 2005-2006, the course has renewed contents and it is no longer possible to do an examination based on the old contents.
• The course can be seen as a follow-up to the HDL-Based SoC Design module of the System-on-Chip Design course. It is also open to students with an equivalent preparation, such as the ASIC Design Laboratory.

Contents

• Low-power design techniques at the system and register-transfer levels.
• Asynchronous design.
• Advanced verification: formal verification, testbench design, transaction-level modeling, SystemC.
• Advanced architectures, such as networks-on chip.

Compulsory Material

• A series of papers and books as specified below.
• The slides of the lectures (see below).

List of papers and books

1. Pedram, M., Power Minimization in IC Design: Principles and Applications, ACM Transactions on Design Automation of Electronic Systems, Vol. 1(1), (January 1996). On-line copy (only in UT-domain).
2. Pedram, M. and A. Abdollahi, Low-Power RT-Level Synthesis Techniques: A Tutorial, IEE Proceedings on Computers and Digital Techniques, Vol. 152(3), pp 333-343, (May 2005). On-line copy (only in UT-domain).
3. Benini, L., G. De Micheli and E. Macii, Designing Low-Power Circuits: Practical Recipes, IEEE Circuits and Systems Magazine, Vol. 1(1), pp 6-25, (2001). On-line copy (only in UT-domain).
4. Verbauwhede, I. and C. Nicol, Low Power DSPs for Wireless Communications, International Symposium on Low-Power Electronic Design, ISLPED'00, Rapallo, Italy, pp 303-310, (2000). On-line copy (only in UT-domain).
5. Sparsoe, J. and S. Furber (Eds.), Principles of Asynchronous Circuit Design, A Systems Perspective, Kluwer Academic Publishers, Boston, (2001). The first 8 chapters can be downloaded from Jens Sparsoe's home page. To be studied: Chapters 1, 2, 3, Sections 4.1, 4.2, Chapter 5, Sections 7.1, 8.3, and 8.4.
6. Berkel, K. van , J. Kessels, M. Roncken, R. Seijs and F. Schalij, The VLSI-Programming Language Tangram and Its Translation into Handshake Circuits, European Conference on Design Automation, EDAC'91, pp 384-389, (1991). On-line copy (only in UT-domain).
7. Peeters, A. and K. van Berkel, Single-Rail Handshake Circuits, Second Working Conference on Asynchronous Design Methodologies, pp 53-62, (May 1995). On-line copy (only in UT-domain).
8. Peeters, A., Single-Rail Handshake Circuits, Ph.D. Thesis, Eindhoven University of Technology, Institute for Programming Research and Algorithmics (TUE-IPA), (June 1996). On-line copy. This material is optional, only meant for background reading.

Own Slides

Topic	Release Date
Organization	April 25, 2006
Low-power design	April 25, 2006
Low-power design, Part 2	May 1, 2006
Asynchronous systems, Part 1	May 8, 2006
Asynchronous systems, Part 2	May 15, 2006
Asynchronous systems, Part 3	May 22, 2006
Verification	May 29, 2006

External Slides

Topic	Source
SystemC	Bernhard Niemann, SystemC 1.x Introduction and Tutorial, 4th European SystemC Users Group Meeting, 2001.

Examination and projects

The following projects need to be carried out (you are allowed to propose alternative projects):

• POW: Power Estimation and Low-Power Design.
• ASY: Asynchronous Design

The examination consists of a discussion on your project results and an oral examination on the entire theory. You will receive separate marks for each project. The average of the two marks is your base mark. Your performance in the theory part of the oral examination will be used to correct the base mark at most by one point (up or down) to become the final mark.

Links

• Background-Reading Book List on VLSI.