• To gain practical experience with VHDL (or to refresh the existing knowledge).
• To become familiar with the Modelsim VHDL simulator. Modelsim is one of the most powerful VHDL/Verilog simuators that are currently available. It is a product of Model Technology. The University of Twente has access to these tools through its membership of Europractice, an initiative of the European Union that provides IC design facilities to universities and research institutes.

The greatest commondivider (GCD) circuit that is the topic of this exercise, is presented in a document entitled VHDL for Synthesis and Simulation. It is strongly recommended to have read that document before doing any of the exercises.

Exercise VHD-1: Compile and Simulate the GCD's register-transfer level (RTL) Description

Create a new Modelsim project and add the following files to it:

• gcd-ent.vhd: the entity declaration of the GCD circuit.
• gcd-rtl-arch.vhd: the description of the architecture rtl of the GCD circuit.
• tb-gcd.vhd: the entities and architectures of the testbench for the GCD circuit.
• tb-gcd-rtl-conf.vhd: the configuration declaration that combines the testbench and the rtl architecture of the GCD circuit (this file should be compiled with the VHDL 93 option).

Study the file tb-gcd.vhd and pay especially some attention to the architecture behavioral of the entity testvec_gcd. You should see that the inputs for the simulation are taken from a file gcd.in that contains pairs of numbers on each line for which the GCD should be calculated. You can modify this file if you want.

Run a simulation and generate waveforms that clearly show that circuit functions as intended.

Exercise VHD-2: Complete the Structural Description and Simulate

Before doing any simulations, you will first need to complete the controller description as provided in the file gcd-controller.vhd. It is incomplete: only the next-state computation and output values for the first state is given. You will have to provide the descriptions for the missing states.

Add the following files to the project of exercise VHD-1 and then compile:

• int-sub.vhd: the subtractor;
• int-comp.vhd: the comparator;
• int-mux.vhd: the multiplexer;
• int-reg.vhd: the register;
• gcd-controller.vhd: the controller as completed by you;
• gcd-structure-arch.vhd: the structural architecture of the GCD that instatiates the blocks above and interconnects them;
• gcd-conf-combine.vhd: the configration for the structural GCD description;
• tb-gcd-struct-conf.vhd: the configuration that binds the structural GCD description with the testbench.

Deliverables

• Your version of the file gcd-controller.vhd.
• A printout of waveforms that clearly shows that the circuit with your controller correctly calculates GCDs. Apart from the correct input-output behavior for one representative GCD calculation, the waveforms should also show the values of the registers holding the intermediate integers and the sequence of states that the controller subsequently assumes.