Project TRA: Data-Flow-Graphs Transformations

This project is a compulsory part of the examination for the Implementation of Digital Signal Processing course at the University of Twente. The goals of this project are:

Preliminaries

This project is a continuation of Project MAP. The DFG to be used is the second-order IIR filter of that project. For the Arx exercises, the files provided for Project MAP should be used as a starting point including the values for the filter coefficients.

Exercise TRA-1: Pipelining and Retiming for Non-Overlapped Scheduling

Consider the second-order IIR filter of project MAP. The intention is to find the fastest possible non-overlapped schedule for the filter as in Exercise MAP-5. However, prior to scheduling, you are requested to apply a sequence of pipelining and retiming transformations to the DFG with the goal of minimizing the critical path. As before, you can assume that a multiplication requires two clock cycles and an addition one. Illustrate each step in the sequence by drawing the intermediate DFGs and the final one.

Next to the primary goal of minimizing the critical path, consider the reduction of hardware resources in the eventual implementation as a secondary optimization goal.

Comment on the effects of the transformation on the critical loop.

Exercise TRA-2: Data-Flow Verification

Verify the correctness of your solution for TRA-1 by creating a model in Arx and simulating it. Use the data-flow coding style as in file sec_df2.arx for this purpose.

When simulating with the same input stream as in MAP-1, do you expect any difference in the output? Motivate your answer and the check whether the actual output stream shows the behavior that you expect.

Exercise TRA-3: One-Step Look-Ahead Transformation

Apply a one-step look-ahead transformation to the original filter. Try to preserve the topology of the DFG as much as possible (given the fact that the original graph has a direct-form II structure, this means that the same structure should be recognizable in the transformed DFG).

Assuming, as usual, that a multiplication requires two clock cycles and an addition one, comment on the effects of the transformation on the critical path and the critical loop.

Exercise TRA-4: Data-Flow Verification

Verify the correctness of your solution for TRA-3 by creating a model in Arx and simulating it. Use the data-flow coding style as in file sec_df2.arx for this purpose. It may happen that the output produced by your solution is slightly different from the output stream produced by the original DFG (why?). Plot this difference in a graph.

Exercise TRA-5: Overlapped Scheduling after Look-Ahead Transformation

Implement the DFG using a rate-optimal overlapped schedule. In MAP-6, the latency was given. Here, you are invited to minimize the latency as a secondary goal (your primary goal being to minimize the number of FUs given the rate-optimal execution speed). First, create a paper design. Then, implement this design in Arx in order to verify its correctness. A necessary condition for correctness is that the output files produced after the simulations of TRA-4 and TRA-5 are identical (except for some possible time shift in the output sequence).

After having observed that the implementation has the expected output, synthesize the new design. Comment on the results comparing the new performance figures to the area and time numbers as reported in Project MAP. Visualize the relation between clock cycles per iteration and area for all versions of the second-order IIR filter encountered in Projects MAP and TRA excluding the "data flow" versions.

Deliverables

Write a short report always motivating your choices and explaining the way you have reached your answers. Do not be verbose. In particular, do not copy the entire project description in your report. On the other hand, be as complete as possible providing details of your solutions by means of diagrams, (data-flow) graphs, tables, etc.

For Exercises involving Arx, supply the Arx code written by you, modified testbench code (if any), waveforms obtained from VHDL or C++ simulations (when applicable), Matlab plots, synthesis results, etc.

Grading

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Last update on: Tue Mar 10 23:20:25 CET 2026 by Sabih Gerez.