Project DAT: Data-Path-and-Controller Systems
This project is a compulsory part of the examination for the
Design course at the University of Twente. The goals of this
Background information on this project can be found in the document
VHDL for Simulation and Synthesis. Please read the section on
data path and controllers of that document before starting to work on this
To become aware of the distinction between the data path and the
controller of a data processing system.
To become aware of the complications involved in mapping an algorithm
on a given data path.
This project has to be carried out in the same directory as project
SYN. Once you have logged in, execute the command
get-module dat syn
to get the files for this proejct in a subdirectory syn
(assuming syn is the name of the directory you used for
Exercise DAT-1: Evaluate Given Data-Path-and-Controller System
The starting point for the data-path-and-controller system is given by
the following files:
First get acquainted with the files and try to understand how the code
Compile the files and perform a simulation of the GCD
computation on the 16-bit data-path-and-controller system as given
in the configuration.
- siso_gen_dpctrl_arch.vhd: a structural architecture for
siso_gen composed of a data path and a controller.
- cmp_add_dp.vhd: the data path with a comparator,
adder/subtractor and memory;
- cmp_add_ctrl_ent.vhd: the controller entity for the given
- cmp_add_ctrl_gcd_arch.vhd: the controller architecture
that implements the GCD algorithm on the data path.
- conf_tb_siso_gen_dpctrl.vhd: the configuration to be able
to simulate this version of siso_gen.
The GCD in project SYN used one clock cycle per iteration of
Euclid's algorithm: the comparison, multiplexing and subtraction
involved all took place within the same clock period. How many clock
cycles are used in one iteration for the implementation on the
data-path-and-controller architecture? Motivate your answer using
the FSM of the controller and prove it by appropriate simulation waveforms.
Exercise DAT-2: Improve the GCD Controller
The provided controller that computes a GCD on the given data path can
be improved. Think of such a solution. First draw the FSM and
calculate the number of clock cycles per iteration. If the algorithm
is not symmetric, i.e. the number of clock cycles is different for the
case that the comparison fails or succeeds (the termination case where
the two operands of the comparison are equal is not relevant), take
the average of the number of clock cycles for the two cases as a
measure for the performance.
Create a new architecture for the controller, called my_gcd
and an appropriate configuration to simulate it. Verify that the GCD
is correctly computed.
Sythesize the improved GCD using a loose constraint (say 10 ns).
Verify that the postsynthesis simulation is also correct.
Exercise DAT-3: New Applications on Given Data Path
Replace the controller to create new application without touching the
data path. Agree with the assistant on one of the following
applications (choose a simple circuit if you are behind schedule):
For each application, perform a presynthesis simulation, synthesize it
with a loose constraint,
and then perform a post-synthesis simulation.
- Blocked two-input addition. This architecture takes a pair
of inputs from the data stream incoming to siso_gen and outputs
their sum on the outgoing data stream.
- Pipelined two-input addition. For each input, this
architecture outputs the sum of this input with its predecessor in the
input data stream.
- Multiplication. The two inputs are restricted to be positive
numbers such that the product still fits within the word length. The
input data stream should start with the constant 1 followed by pairs
of numbers to be multiplied.
- Three-input sort. Use the specification given
in Exercise VHD-4 except for the fact that additional clock cycles may
be necessary to perform all computations.
Prepare a short report that contains:
- The answers to the questions of Exercise DAT-1 and the requested waveform
- The FSM of your improved controller for Exercise DAT-2, as well
as all VHDL code that you have created or modified; the memory
organization (what is stored at which address?); a discussion of
the performance of
your design expressed in clock cycles; waveform plots showing relevant details
of your simulations (presynthesis and postsynthesis).
- For the implemented application in Exercise DAT-3, the same
deliverables as required for Exercise DAT-2.
- At most 2 points can be earned with DAT-1.
- At most 3 points can be earned with DAT-2.
- At most 5 points can be earned with DAT-3. Any of the two-input addition
circuits is worth at most 3 points; any of the other circuits is worth
at most 5 points.
Last update on:
Sun Sep 11 00:36:32 CEST 2016
by Sabih Gerez.