Algorithms for VLSI Design Automation

Programming Project (two persons): Transistor-Chain Construction for CMOS Cell Compilation

Summary: Cell compilation is the process of translating a netlist of transistors into layout. This project deals with CMOS transistor circuits obeying a layout in which pairs of nMOS and pMOS transistors with the same gate signal are located under the same polysilicon strip. Chains of these pairs can be formed by merging the diffusion areas of the transistors. The optimal solution merges the maximal number of diffusion areas and leads in this way to the narrowest cell width. Many algorithms for this problem have been proposed in the literature. This project considers one of them.

Detailed Description

Last update on: Wed Mar 17 23:15:20 MET 1999 by Sabih Gerez.